The present invention relates to a semiconductor design technology; and, more particularly, to an apparatus for transmitting read data from the semiconductor memory device.
A DRAM (dynamic random access memory), which is a representative semiconductor memory device, provides ×4, ×8 and ×16 action modes. These action modes output data using four or eight I/O pins at the same time or output the data using sixteen I/O pins at the same time. Generally, the DRAM has a circuit which is designed based on the ×16 action mode and one of ×4, ×8 and ×16 action mode is selectively applied to the data transmission.
That the data are read out through the ×8 action mode in the DRAM which is designed based on the ×16 action mode is to selectively use eight lines among 16 I/O lines.
In order to achieve this operation in the DRAM, two line groups are required in the data transmission path, for example, first and second global I/O line groups. Also, it is necessary to have a multiplexing unit for selecting transferred data from these two global I/O line groups. Further, to control the multiplexing unit, it is necessary to have an additional column address signal which is an address signal together with a read command.
FIG. 1 is a block diagram illustrating a conventional read transmission path in a semiconductor memory device.
Referring to FIG. 1, in the read transmission path, there are two local I/O lines LIO0 and LIO1, two sense amplifiers 11A and 11B for sensing and amplifying data LIOD0 and LIOD1 which are applied to the two local I/O lines LIO0 and LIO1, two global I/O lines GIO0 and GIO1, a multiplexing unit 12 for selecting one from the data GIOD0 and GIOD1 transferred from the two global I/O lines GIO0 and GIO1 and a latch unit 13 for transferring the latched data DQD to an output terminal DQ. Further, a first control unit 14 to control two sense amplifiers 11A and 11B and a latch unit 13 is provided as well as a second control unit 15 to control the multiplexing unit 12.
Even though two local I/O lines LIO0 and LIO1 and two sense amplifiers 11A and 11B are illustrated, a plurality of local I/O lines and sense amplifiers can be provided. That is, the local I/O lines and the sense amplifiers corresponding to the local I/O lines are limited to two in numbers for the sake of convenience.
Meanwhile, the data processing in the read operation will be illustrated below.
When the read command is inputted to the DRAM, the data LIOD0 and LIOD1 stored in the memory cell are applied to the sense amplifiers 11A and 11B through the local I/O lines LIO0 and LIO1.
A control signal IOSTBP0 or IOSTBP1 for the individual sense amplifier 11A or 11B is produced in response to a column select signal YI produced based on a burst action, which is a signal to select a column in the memory cell and corresponds to a write command, and the data LIOD0 and LIOD1 on the I/O lines LIO0 and LIO1 are applied to the global I/O line GIO0 or GIO1 in response to the control signal IOSTBP0 or IOSTBP1.
Subsequently, the data GIOD0 and GIOD1 of the global I/O lines GIO0 and GIO1 reach to the multiplexing unit 12 and one of these data GIOD0 and GIOD1 is selected in response to a multiplexing control signal GY9 which is produced in response to the column address signal Y9 which is a signal having a column address information of the memory cell and corresponds to the read command. The selected data SELD is transferred to the latch unit 13.
The selected data SELD which is transferred to the latch unit 13 is transferred to the output terminal DQ in response to a latch control signal PINSTB which is generated in response to the column select signal YI.
FIG. 2 is a timing chart illustrating an operation of a circuit existing on the read transmission path of FIG. 1. Assuming that burst length is 2 and the read command is inputted four times, the column address signal Y9 undergoes a level transition in response to the input of each of the read commands READ1 to READ4 and the column select signal YI starts the toggling in the level transition based on the write command which is inputted together with the read commands READ1 to READ4.
When the column address signal Y9 is a logic low level, the data GIOD0 is loaded to the first global I/O line GIO0. When the column address signal Y9 is a logic high level, the data GIOD1 is loaded to the second global I/O line GIO1. This operation is controlled by the control signals IOSPBP0 and IOSTBP1 of the sense amplifiers 11A and 11B.
In FIG. 2, the dotted line in the waveform of data GIOD0 and GIOD1 loaded to the global I/O lines GIOO and GIO1 represents the latch operation of the previous value as a meaningless level.
Next, the multiplexing unit 12 selects one from the data GIOD0 and GIOD1, which are loaded to the two global I/O lines GIOO and GIO1, in response to the multiplexing control signal GY9 and transfers the selected data to the latch unit 13. The latch unit 13 transfers the data to the output terminal DQ in response to the latch control signal PINSTB.
On the other hand, a point of time data stored in the memory cell is read out is determined by the column select signal YI. Therefore, the timing of the column select signal YI frequently changes in order to meet the data read timing. As a result, the timing of the control signals IOSTBP0, IOSTBP1 and PINSTB, which are generated in response to the column select signal YI, may also change.
That is, both the transmission timing of the data LIODO and LIOD1, which are delivered to the global I/O lines GIO0 and GIO1 from the local I/O lines LIO0 and LIO1, and the transmission timing of the data DQD from the latch unit 13 may change. However, in the situation where the transmission timing of data is changed by the sense amplifier 11 and latch unit 13, there are some problems because the transmission timing of the multiplexing unit 12 which is located in the center of the transmission does not change.
That is, since the first control unit 14, which uses the column select signal YI as a source signal, and the second control unit 15, which uses the column address signal Y9 as a source signal, are unable to work mutually, the devices (reference numerals 11 to 13) do not work in synchronization with each other.
FIG. 3 illustrates this problem of the read transmission path.
Referring to FIG. 3, in order to meet the read timing of the data, the read data GIOD0′ and GIOD1′ are loaded to the global I/O lines GIO0 and GIO1 with a delay time according to a delayed column select signal YI′ in an activation time. Subsequently, the data GIOD0′ and GIOD1′ are selected in response to the multiplex control signal GY9. At this time, there is a difference (A) in waveform between the selected data SED′ and the data GIOD0′ and GIOD1′, which are transferred to the global I/O lines GIOO and GIO1, wherein the dotted line represents the latch operation of the previous value as a meaningless level. The waveform difference between the two data GIOD0′ and GIOD1′ is caused by the difference in synchronization between the operations of the sense amplifier 11 and the multiplexing unit 12.
The data SELD′ outputted from the multiplexing unit 12 are delivered to the output terminal DQ in response to the latch control signal PINSTB′. At this time, since the latch control signal PINSTB′ uses the column select signal YI as a source signal, the data SELD′ are delivered to the output terminal DQ with a predetermined delay time. Therefore, there is a difference (B) in waveform between the data SED′ from the multiplexing unit 12 and the data DQD′ from the latch unit 13. The reason why the waveform difference is caused is that the multiplexing unit 12 and the latch unit 13 are not synchronized with each other. Here, the difference of the waveform, as mentioned above, means a difference in timing of a rising edge and a falling edge.
The problems motioned above are as follows: first, the synchronization of the multiplexing unit 12 and the sense amplifier 11 does not match with each other and second, the synchronization of the latch unit 13 and the multiplexing-unit 12 does not match with each other. These problems are caused based on that the source signals Y1 and Y9 of the control units 14 and 15, which respectively control the sense amplifier 11, the multiplexing unit 12 and the latch unit 13, are different from each other.